Several intellectual property (IP) cells are available in the market to implement 8051-compliant CPUs, which are widely employed in embedded systems for microcontroller applications. Yet they frequently lack features that have become a key point in such systems, like power optimization. This paper focuses on minimizing the switching activity of an 8051 IP core, through RTL (Register Transfer Level) techniques such as state encoding, clock gating and operand isolation, with the aim to keep unaltered CPU performances. This approach preserve the IP high-reusability and technology independence, as it only consists of modifications to the source VHDL code. As results a total power reduction of about 40% has been achieved, with limited area overhead.
8051 CPU Core Optimization for Low Power at Register Transfer Level
SAPONARA, SERGIO;FANUCCI, LUCA
2005-01-01
Abstract
Several intellectual property (IP) cells are available in the market to implement 8051-compliant CPUs, which are widely employed in embedded systems for microcontroller applications. Yet they frequently lack features that have become a key point in such systems, like power optimization. This paper focuses on minimizing the switching activity of an 8051 IP core, through RTL (Register Transfer Level) techniques such as state encoding, clock gating and operand isolation, with the aim to keep unaltered CPU performances. This approach preserve the IP high-reusability and technology independence, as it only consists of modifications to the source VHDL code. As results a total power reduction of about 40% has been achieved, with limited area overhead.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
