Despite recent advances in the microelectronics technology, the implementation of high-throughput decoders for LDPC codes remains a challenging task. This paper aims at summarising the top-down design flow of a decoder for a structured LDPC code compliant with the WWiSE proposal for WLAN. Starting from the system performance analysis with finite-precision arithmetic, a high-throughput architecture is presented as an enhancement of the state-of-the-art solutions, and its VLSI design detailed. The envisaged architecture is also very flexible as it supports several code rates with no significant hardware overhead. The overall decoder, synthesised on 0.18 μm standard cells CMOS technology, showed remarkable performances: small implementation loss (0.2 dB down to BER = 10 -8), low latency (less than 6.0 μs), high useful throughput (up to 940Mbps) and low complexity (about 375 Kgates).
VLSI Design of a High–Throughput Multi–Rate Decoder for Structured LDPC Codes
FANUCCI, LUCA
2005-01-01
Abstract
Despite recent advances in the microelectronics technology, the implementation of high-throughput decoders for LDPC codes remains a challenging task. This paper aims at summarising the top-down design flow of a decoder for a structured LDPC code compliant with the WWiSE proposal for WLAN. Starting from the system performance analysis with finite-precision arithmetic, a high-throughput architecture is presented as an enhancement of the state-of-the-art solutions, and its VLSI design detailed. The envisaged architecture is also very flexible as it supports several code rates with no significant hardware overhead. The overall decoder, synthesised on 0.18 μm standard cells CMOS technology, showed remarkable performances: small implementation loss (0.2 dB down to BER = 10 -8), low latency (less than 6.0 μs), high useful throughput (up to 940Mbps) and low complexity (about 375 Kgates).I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
