Modelling and measurements of thermomechanical stress induced drift on polysilicon resistors with different layout

In this work, we study the effects of packaging-and reflow soldering-induced thermomechanical stress on the value of a p-type polysilicon resistor. We perform finite element multiscale simulations that, differently from previous works on this subject, take into account also the contributions to the stress of the surroundings of the devices, including vias, metal lines and polysilicon dummy modules. In order to enable computationally efficient simulations with the required micrometric resolution, we develop a two-stage approach, where a first package-level model is solved to provide the input for a finer scale model. We consider two different layouts for the resistor: a classic rectangular one and an 'L-shaped' one, which are compared on the basis of their sensitivity to the thermally induced stress. The resistance experiments a drift of -3.3% in the case of the rectangular layout and of -0.77% in the case of the L-layout. The greater robustness of the L-resistor to the reflow soldering process is confirmed by experimental results performed on a purposely-designed test chip, alongside the capability of our model to predict the trend of the stress induced resistance drift.