| Nome |
# |
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ROS/Gazebo Based Simulation of Co-operative UAVs, file e0d6c930-b66f-fcf8-e053-d805fe0aa794
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2.823
|
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SRAM-Based FPGA Systems for Safety-Critical Applications: A Survey on Design Standards and Proposed Methodologies, file e0d6c92d-2763-fcf8-e053-d805fe0aa794
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450
|
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Cross-level Co-simulation and Verification of an Automatic Transmission Control on Embedded Processor, file e0d6c931-7b3d-fcf8-e053-d805fe0aa794
|
307
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A PVS-Simulink Integrated Environment for Model-Based Analysis of Cyber-Physical Systems, file e0d6c92c-67e4-fcf8-e053-d805fe0aa794
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236
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Verifying data secure flow in AUTOSAR models, file e0d6c930-7d1d-fcf8-e053-d805fe0aa794
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233
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Using smartwatch sensors to support the acquisition of sleep quality data for supervised machine learning, file e0d6c92d-1364-fcf8-e053-d805fe0aa794
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224
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ASSESS: A Simulator of Soft Errors in the Configuration Memory of SRAM-Based FPGAs, file e0d6c92d-2d1e-fcf8-e053-d805fe0aa794
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206
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Verifying safety properties of a nonlinear control by interactive theorem proving with the Prototype Verification System, file e0d6c92d-33fb-fcf8-e053-d805fe0aa794
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171
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UA2TPG: An untestability analyzer and test pattern generator for SEUs in the configuration memory of SRAM-based FPGAs, file e0d6c92d-1adc-fcf8-e053-d805fe0aa794
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162
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Logic-Based Formalization of System Requirements for Integrated Clinical Environments, file e0d6c92d-b9f4-fcf8-e053-d805fe0aa794
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157
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The benefits of using interactive device simulations as training material for clinicians: an experience report with a contrast media injector used in CT, file e0d6c92d-5bf5-fcf8-e053-d805fe0aa794
|
150
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null, file e0d6c92d-1172-fcf8-e053-d805fe0aa794
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149
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Detecting elderly behavior shift via smart devices and stigmergic receptive fields, file e0d6c92d-1358-fcf8-e053-d805fe0aa794
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139
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Integrated Simulation of Implantable Cardiac Pacemaker Software and Heart Models, file e0d6c926-4435-fcf8-e053-d805fe0aa794
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132
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null, file e0d6c92c-b017-fcf8-e053-d805fe0aa794
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130
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Verifying Data Secure Flow in AUTOSAR Models by Static Analysis, file e0d6c92a-5193-fcf8-e053-d805fe0aa794
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128
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Exploiting Model Checking for Mobile Botnet Detection, file e0d6c92e-1f6a-fcf8-e053-d805fe0aa794
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116
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Application of Model Checking to Fault Tolerance Analysis, file e0d6c92d-c0a5-fcf8-e053-d805fe0aa794
|
112
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null, file e0d6c92c-b155-fcf8-e053-d805fe0aa794
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108
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Modeling and simulation of attacks on cyber-physical systems, file e0d6c930-ab28-fcf8-e053-d805fe0aa794
|
85
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Towards a Formalization of System Requirements for an Integrated Clinical Environment, file e0d6c927-0a4a-fcf8-e053-d805fe0aa794
|
83
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Extending a user interface prototyping tool with automatic MISRA~C code generation, file e0d6c928-b479-fcf8-e053-d805fe0aa794
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77
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Formalization and co-simulation of attacks on cyber-physical systems, file e0d6c92e-8a2e-fcf8-e053-d805fe0aa794
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77
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Co-simulation of semi-autonomous systems: The line follower robot case study, file e0d6c92f-9ae3-fcf8-e053-d805fe0aa794
|
64
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OLT(RE)2: an On-Line on-demand Testing approach for permanent Radiation Effects in REconfigurable systems, file e0d6c930-7d01-fcf8-e053-d805fe0aa794
|
51
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Demo: Co-simulation of UAVs with INTO-CPS and PVSio-web, file e0d6c92f-e561-fcf8-e053-d805fe0aa794
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28
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Modeling communication network requirements for an integrated clinical environment in the Prototype Verification System, file e0d6c930-bbe8-fcf8-e053-d805fe0aa794
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26
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Towards Stochastic FMI Co-Simulations: Implementation of an FMU for a Stochastic Activity Networks Simulator, file e0d6c92f-ab95-fcf8-e053-d805fe0aa794
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22
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Formal verification in the loop to enhance verification of safety-critical cyber-physical systems, file e0d6c92e-1f6c-fcf8-e053-d805fe0aa794
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16
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Adapting the duty cycle to traffic load in a preamble sampling MAC for WSNs: formal specification and performance evaluation, file e0d6c927-2e04-fcf8-e053-d805fe0aa794
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15
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Data leakage in Java applets with exception mechanism, file e0d6c92f-d769-fcf8-e053-d805fe0aa794
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13
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SEU-X: a SEu Un-eXcitability prover for SRAM-FPGAs, file e0d6c92a-ef08-fcf8-e053-d805fe0aa794
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12
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null, file e0d6c92a-a52f-fcf8-e053-d805fe0aa794
|
11
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Design and Safety Verification of a Distributed Charge Equalizer for
Modular Li-ion Batteries, file e0d6c926-46d3-fcf8-e053-d805fe0aa794
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9
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null, file e0d6c92c-fd8b-fcf8-e053-d805fe0aa794
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8
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Failure Probability of SRAM-FPGA Systems with Stochastic Activity Networks, file e0d6c92a-f9c0-fcf8-e053-d805fe0aa794
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6
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ReLock: a resilient two-phase locking RESTful transaction model, file e0d6c931-558c-fcf8-e053-d805fe0aa794
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6
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Block-Based Models and Theorem Proving in Model-Based Development, file e0d6c931-986a-fcf8-e053-d805fe0aa794
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6
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A framework for FMI-based co-simulation of human–machine interfaces, file e0d6c92e-4311-fcf8-e053-d805fe0aa794
|
5
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null, file e0d6c92c-9005-fcf8-e053-d805fe0aa794
|
4
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OLT(RE)2: an On-Line on-demand Testing approach for permanent Radiation Effects in REconfigurable systems, file e0d6c930-7adb-fcf8-e053-d805fe0aa794
|
4
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JCSI: A Tool for Checking Secure Information Flow in Java Card Applications, file e0d6c92c-61fd-fcf8-e053-d805fe0aa794
|
3
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Combining PVSio with Stateflow, file e0d6c92c-6616-fcf8-e053-d805fe0aa794
|
3
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Verifying data secure flow in AUTOSAR models, file e0d6c930-a4e5-fcf8-e053-d805fe0aa794
|
3
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A logic theory pattern for linearized control systems, file e0d6c931-a581-fcf8-e053-d805fe0aa794
|
3
|
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Training Neural Networks in Cyber-Physical Systems using Design Space Exploration and Co-Simulation, file 497cde55-275e-4934-8b3e-650f9acb8620
|
2
|
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A Formal Verification Environment for Railway Signalling System Design, file e0d6c925-e9f7-fcf8-e053-d805fe0aa794
|
2
|
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Formally verifying fault tolerant system designs, file e0d6c926-22a1-fcf8-e053-d805fe0aa794
|
2
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Checking secure information flow in Java bytecode by code transformation and standard bytecode verification, file e0d6c926-2560-fcf8-e053-d805fe0aa794
|
2
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Using AUTOSAR high-level specifications for the synthesis of security components in automotive systems, file e0d6c92c-7239-fcf8-e053-d805fe0aa794
|
2
|
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null, file e0d6c92c-9002-fcf8-e053-d805fe0aa794
|
2
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Java bytecode verification for secure information flow, file e0d6c92c-a56a-fcf8-e053-d805fe0aa794
|
2
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|
Formal verification and co-simulation in the design of a synchronous motor control algorithm, file e0d6c92f-3da2-fcf8-e053-d805fe0aa794
|
2
|
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UA2TPG: An untestability analyzer and test pattern generator for SEUs in the configuration memory of SRAM-based FPGAs, file e0d6c930-6183-fcf8-e053-d805fe0aa794
|
2
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|
A PVS-Simulink Integrated Environment for Model-Based Analysis of Cyber-Physical Systems, file e0d6c930-64d9-fcf8-e053-d805fe0aa794
|
2
|
|
null, file e0d6c930-81e5-fcf8-e053-d805fe0aa794
|
2
|
|
SRAM-Based FPGA Systems for Safety-Critical Applications: A Survey on Design Standards and Proposed Methodologies, file e0d6c930-a32c-fcf8-e053-d805fe0aa794
|
2
|
|
ROS/Gazebo Based Simulation of Co-operative UAVs, file e0d6c930-b66e-fcf8-e053-d805fe0aa794
|
2
|
|
A prototyping process for medical devices and systems, file e0d6c931-6d8c-fcf8-e053-d805fe0aa794
|
2
|
|
Co-simulation and Formal Verification of Co-operative Drone Control With Logic-Based Specifications, file e0d6c931-6fbc-fcf8-e053-d805fe0aa794
|
2
|
|
A framework for formal analysis and simulative evaluation of security attacks in wireless sensor networks, file e0d6c931-71e3-fcf8-e053-d805fe0aa794
|
2
|
|
Using Control Dependencies for Space-Aware Bytecode Verification, file e0d6c926-19e5-fcf8-e053-d805fe0aa794
|
1
|
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Decomposing Bytecode Verification by Abstract Interpretation, file e0d6c926-1f0b-fcf8-e053-d805fe0aa794
|
1
|
|
Concrete and Abstract Semantics to Check Secure Information Flow in Concurrent Programs, file e0d6c926-21a7-fcf8-e053-d805fe0aa794
|
1
|
|
Application of a Genetic Algorithm for Testing SEUs in SRAM-FPGA Systems, file e0d6c926-360f-fcf8-e053-d805fe0aa794
|
1
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Formal approaches to SEUs testing in FPGAs, file e0d6c926-3c4a-fcf8-e053-d805fe0aa794
|
1
|
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Analysing Information Flow Properties in Assembly Code by Abstract Interpretation, file e0d6c926-3f4b-fcf8-e053-d805fe0aa794
|
1
|
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Mitigation of Single Event Upsets in the control logic of a charge
equalizer for Li-ion batteries, file e0d6c926-46d4-fcf8-e053-d805fe0aa794
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1
|
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An Inter-Processor Communication Interface for Data-Flow Centric Heterogeneous Embedded Multiprocessor Systems, file e0d6c92a-1f21-fcf8-e053-d805fe0aa794
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1
|
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PyXEL: An Integrated Environment for the Analysis of Fault Effects in SRAM-Based FPGA Routing, file e0d6c92f-1032-fcf8-e053-d805fe0aa794
|
1
|
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null, file e0d6c92f-6087-fcf8-e053-d805fe0aa794
|
1
|
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Analysis of security attacks in wireless sensor networks: From UPPAAL to Castalia, file e0d6c92f-76e0-fcf8-e053-d805fe0aa794
|
1
|
|
Co-simulation of bio-inspired multi-agent algorithms, file e0d6c930-578e-fcf8-e053-d805fe0aa794
|
1
|
|
null, file e0d6c930-6b81-fcf8-e053-d805fe0aa794
|
1
|
|
Extending a user interface prototyping tool with automatic MISRA~C code generation, file e0d6c930-7a53-fcf8-e053-d805fe0aa794
|
1
|
|
Verifying safety properties of a nonlinear control by interactive theorem proving with the Prototype Verification System, file e0d6c930-c1ac-fcf8-e053-d805fe0aa794
|
1
|
|
null, file e0d6c930-caaa-fcf8-e053-d805fe0aa794
|
1
|
| Totale |
6.821 |