ZULBERTI, LUCA Statistiche

ZULBERTI, LUCA  

DIPARTIMENTO DI INGEGNERIA DELL'INFORMAZIONE  

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Risultati 1 - 14 di 14 (tempo di esecuzione: 0.069 secondi).
Titolo Data di pubblicazione Autore(i) File
A PUF-Based Secure Boot for RISC-V Architectures 1-gen-2024 DI MATTEO, Stefano; Zulberti, Luca; Cosimo Lapenna, Federico; Nannipieri, Pietro; Crocetti, Luca; Fanucci, Luca; Saponara, Sergio
Cycle-Accurate Verification of the Cryptographic Co-Processor for the European Processor Initiative 1-gen-2024 Nannipieri, Pietro; DI MATTEO, Stefano; Crocetti, Luca; Zulberti, Luca; Fanucci, Luca; Saponara, Sergio
Exploiting FPGA Dynamic Partial Reconfiguration for a Soft GPU-based System-on-Chip 1-gen-2023 Monopoli, M; Zulberti, L; Todaro, G; Nannipieri, P; Fanucci, L
Exploring Key Aspects of Soft GPGPU Computing for On-board Acceleration of Artificial Intelligence Algorithms in Space Applications 1-gen-2023 Monopoli, M.; Zulberti, L.; Nannipieri, P.; Fanucci, L.; Moranti, S.
Highly Parameterised CGRA Architecture for Design Space Exploration of Machine Learning Applications Onboard Satellites 1-gen-2023 Zulberti, L.; Monopoli, M.; Nannipieri, P.; Fanucci, L.; Moranti, S.
Inference and Evaluation of Deep Convolutional Neural Networks on Microchip's Hardware Accelerator VectorBlox 1-gen-2023 Dada', M.; Zulberti, L.; Nannipieri, P.; Fanucci, L.; Moranti, S.
A Script-Based Cycle-True Verification Framework to Speed-Up Hardware and Software Co-Design: Performance Evaluation on ECC Accelerator Use-Case 1-gen-2022 Zulberti, Luca; DI MATTEO, Stefano; Nannipieri, Pietro; Saponara, Sergio; Fanucci, Luca
Architectural Implications for Inference of Graph Neural Networks on CGRA-based Accelerators 1-gen-2022 Zulberti, Luca; Monopoli, Matteo; Nannipieri, Pietro; Fanucci, Luca
ICU4SAT: A General-Purpose Reconfigurable Instrument Control Unit Based on Open Source Components 1-gen-2022 Nannipieri, Pietro; Giuffrida, Gianluca; Diana, Lorenzo; Panicacci, Silvia; Zulberti, Luca; Fanucci, Luca; Gerardo Munoz Hernandez, Hector; Hubner, Michael
SystemVerilog UVM-based Verification Environment for a SpaceFibre Router 1-gen-2022 Gigli, L.; Nannipieri, P.; Zulberti, L.; Vagaggini, S.; Fanucci, L.
VLSI Design of Advanced-Features AES Cryptoprocessor in the Framework of the European Processor Initiative 1-gen-2022 Nannipieri, P.; Matteo, S. D.; Baldanzi, L.; Crocetti, L.; Zulberti, L.; Saponara, S.; Fanucci, L.
A RISC-V Post Quantum Cryptography Instruction Set Extension for Number Theoretic Transform to Speed-Up CRYSTALS Algorithms 1-gen-2021 Nannipieri, P.; Di Matteo, S.; Zulberti, L.; Albicocchi, F.; Saponara, S.; Fanucci, L.
A Script-Based Cycle-True Verification Framework to Speed-Up Hardware and Software Co-Design of System-on-Chip exploiting RISC-V Architecture 1-gen-2021 Zulberti, Luca; Nannipieri, Pietro; Fanucci, Luca
VLSI Design of Advanced-Features AES Cryptoprocessor in the Framework of the European Processor Initiative 1-gen-2021 Nannipieri, P.; Matteo, S. D.; Baldanzi, L.; Crocetti, L.; Zulberti, L.; Saponara, S.; Fanucci, L.