Performance of a high-throughput tracking processor implemented on Stratix-V FPGA

Two of the biggest challenges for future HEP experiments at hadron colliders are triggering and track reconstruction of high-multiplicity events, where collisions have multiple primary vertices. The highly-non-linear scaling of computing power required for these tasks encourages the adoption of non-traditional, specialized architectures. Amongst them, the “artificial retina” approach, inspired by the architecture of the vision system in the living brain, promises large efficiency of hardware utilization, low-power and low-latency when implemented in state-of-art FPGA devices. The INFN-RETINA project has been a 3-year effort dedicated to investigate the potential of that approach in a real-time tracking processor at Level-0 of the LHC HEP experiments. We present results from studies performed on a prototype system capable of carrying out track reconstruction in a generic 6-layer silicon-strip detector with sub-μs latency at an event rate in excess of 30 MHz, and how a large-scale system can be implemented on multiple boards interconnected with high-speed optical links. Possible applications to real experimental environments will be also discussed.