In the framework of the upgrade of the MEG experiment a new trigger system with demanding performances in terms of latency was designed. To achieve the goal of 512 ns latency the serial connections between trigger boards have been optimized so that they only rely on serial to parallel shift registers for the data flow, minimizing the amount of logic to be crossed by data. A dedicated Finite State Machine (FSM) was designed to select the sampling point of the serial stream with respect to an external precision clock used by both transmitter and receiver. As a proof of concept a 16000 channel weighted waveform sum including pedestal suppression, was computed, resulting in 700 ns of latency.
Low latency serial communication for MEG II trigger system
Francesconi M.;Cei F.;Chiappini M.;Galli L.;Morsani F.;Nicolo D.;Papa A.;Signorelli G.
2019-01-01
Abstract
In the framework of the upgrade of the MEG experiment a new trigger system with demanding performances in terms of latency was designed. To achieve the goal of 512 ns latency the serial connections between trigger boards have been optimized so that they only rely on serial to parallel shift registers for the data flow, minimizing the amount of logic to be crossed by data. A dedicated Finite State Machine (FSM) was designed to select the sampling point of the serial stream with respect to an external precision clock used by both transmitter and receiver. As a proof of concept a 16000 channel weighted waveform sum including pedestal suppression, was computed, resulting in 700 ns of latency.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
