Three different bias strategies aimed to reduce the effect of tuning on either the differential input range or the common-mode range of triode-region CMOS transconductors are presented. The method is applied to an original transconductor topology that is optimized to produce ultralow values. A prototype circuit, which was designed with the 0.35- m bipolar-CMOS-DMOS (BCD6) process of STMicroelectronics, is presented. The effectiveness and limitations of the method are characterized by means of electrical simulations.
CMOS Transconductors With Nearly Constant Input Ranges Over Wide Tuning Intervals
BRUSCHI, PAOLO;
2006-01-01
Abstract
Three different bias strategies aimed to reduce the effect of tuning on either the differential input range or the common-mode range of triode-region CMOS transconductors are presented. The method is applied to an original transconductor topology that is optimized to produce ultralow values. A prototype circuit, which was designed with the 0.35- m bipolar-CMOS-DMOS (BCD6) process of STMicroelectronics, is presented. The effectiveness and limitations of the method are characterized by means of electrical simulations.File in questo prodotto:
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