Three different bias strategies aimed to reduce the effect of tuning on either the differential input range or the common-mode range of triode-region CMOS transconductors are presented. The method is applied to an original transconductor topology that is optimized to produce ultralow values. A prototype circuit, which was designed with the 0.35- m bipolar-CMOS-DMOS (BCD6) process of STMicroelectronics, is presented. The effectiveness and limitations of the method are characterized by means of electrical simulations.
|Autori:||BRUSCHI P; SEBASTIANO F; NIZZA N|
|Titolo:||CMOS Transconductors With Nearly Constant Input Ranges Over Wide Tuning Intervals|
|Anno del prodotto:||2006|
|Digital Object Identifier (DOI):||10.1109/TCSII.2006.882126|
|Appare nelle tipologie:||1.1 Articolo in rivista|