At the High Energy Accelerator Research Organization (KEK) in Tsukuba, Japan, the double-sided silicon strip sub-detector of the Belle II experiment is read out by 1748 APV25 chips. FPGAs perform several calculations on the digitized signals. One of them will be "Hit Time Finding": the determination of the time and amplitude of the signal peaks of each event in real time using pre-programmed neural networks. This work analyses the possibility, precision and reliability of these calculations depending on various parameters.
Machine learning: Hit time finding with a neural network
Batignani G.;Bertacchi V.;Bettarini S.;Bosi F.;Casarosa G.;de Nuccio M.;Forti F.;Lueck T.;Martini A.;Paladino A.;Paoloni E.;Rizzo G.;Zani L.
2019-01-01
Abstract
At the High Energy Accelerator Research Organization (KEK) in Tsukuba, Japan, the double-sided silicon strip sub-detector of the Belle II experiment is read out by 1748 APV25 chips. FPGAs perform several calculations on the digitized signals. One of them will be "Hit Time Finding": the determination of the time and amplitude of the signal peaks of each event in real time using pre-programmed neural networks. This work analyses the possibility, precision and reliability of these calculations depending on various parameters.File in questo prodotto:
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