A two-stage switched-capacitor integrator for high gain inverter-like architectures

A discrete-time, switched capacitor integrator is presented. The integrator is based on a two-stage architecture where the first stage converts the input voltage into a charge that is accumulated into the second stage. The main strength of the proposed circuit is a higher dc gain with respect to previous solutions, making it optimal for low-voltage inverter-like integrators. A further advantage is the fact that, in contrast with existing solutions, the output voltage is valid across the whole clock cycle. Theoretical analysis of the circuit is performed to calculate the dependence of the integrator dc gain and input-referred offset voltage on the corresponding parameters of the constituting amplifiers. Discrete-time simulations are performed to estimate the gain and phase error with respect to an ideal integrator. The results of electrical simulations performed on an inverter-like prototype, designed with the UMC 0.18-μm CMOS process, are presented to show the impact of non-idealities from the amplifiers and switches.