A process for fabricating a device based on tunneling through a very thin vertical silicon membrane is presented. The process has been developed on a < 110 > oriented silicon wafer using high resolution e-beam lithography and KOH anisotropic etching to define the structure. A single evaporation step allows the fabrication of both the source-drain contacts and a control gate self aligned to the top of the silicon membrane. A vertical silicon membrane with a thickness of 15 nm has been obtained. (c) 2006 Elsevier B.V. All rights reserved.
A fabrication process for a silicon tunnel barrier with self-aligned gate
PENNELLI, GIOVANNI;Piotto M.
2006-01-01
Abstract
A process for fabricating a device based on tunneling through a very thin vertical silicon membrane is presented. The process has been developed on a < 110 > oriented silicon wafer using high resolution e-beam lithography and KOH anisotropic etching to define the structure. A single evaporation step allows the fabrication of both the source-drain contacts and a control gate self aligned to the top of the silicon membrane. A vertical silicon membrane with a thickness of 15 nm has been obtained. (c) 2006 Elsevier B.V. All rights reserved.File in questo prodotto:
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