The design of single-stage OTAs for accurate switched-capacitor circuits involves challenging trade-offs between speed and power consumption. The addition of a Slew-Rate Enhancer (SRE) circuit placed in parallel to the main OTA (parallel-type SRE) constitutes a viable solution to reduce the settling time, at the cost of low-power overhead and no modifications of the main OTA. In this work, a practical analytical model has been developed to predict the settling time reduction achievable with OTA/SRE systems and to show the effect of the various design parameters. The model has been applied to a real case, consisting of the combination of a standard folded-cascode OTA with an existing parallel-type SRE solution. Simulations performed on a circuit designed with a commercial 180-nm CMOS technology revealed that the actual settling-time reduction was significantly smaller than predicted by the model. This discrepancy was explained by taking into account the internal delays of the SRE, which is exacerbated when a high output current gain is combined with high power efficiency. To overcome this problem, we propose a simple modification of the original SRE circuit, consisting in the addition of a single capacitor which temporarily boosts the OTA/SRE currents reducing the internal turn-on delay. With the proposed approach a settling-time reduction of 57% has been demonstrated with an SRE that introduces only a 10% power-overhead with respect of the single OTA solution. The robustness of the results have been validated by means of Monte-Carlo simulations.
Performance analysis and design optimization of parallel-type slew-rate enhancers for switched-capacitor applications
Catania A.
;Cicalini M.;Dei M.;Piotto M.;Bruschi P.
2020-01-01
Abstract
The design of single-stage OTAs for accurate switched-capacitor circuits involves challenging trade-offs between speed and power consumption. The addition of a Slew-Rate Enhancer (SRE) circuit placed in parallel to the main OTA (parallel-type SRE) constitutes a viable solution to reduce the settling time, at the cost of low-power overhead and no modifications of the main OTA. In this work, a practical analytical model has been developed to predict the settling time reduction achievable with OTA/SRE systems and to show the effect of the various design parameters. The model has been applied to a real case, consisting of the combination of a standard folded-cascode OTA with an existing parallel-type SRE solution. Simulations performed on a circuit designed with a commercial 180-nm CMOS technology revealed that the actual settling-time reduction was significantly smaller than predicted by the model. This discrepancy was explained by taking into account the internal delays of the SRE, which is exacerbated when a high output current gain is combined with high power efficiency. To overcome this problem, we propose a simple modification of the original SRE circuit, consisting in the addition of a single capacitor which temporarily boosts the OTA/SRE currents reducing the internal turn-on delay. With the proposed approach a settling-time reduction of 57% has been demonstrated with an SRE that introduces only a 10% power-overhead with respect of the single OTA solution. The robustness of the results have been validated by means of Monte-Carlo simulations.File | Dimensione | Formato | |
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