We present a 4-bit power scalable flash analog-to-digital converter in digital 0.18-mum CMOS, targeting low power ultra-wide band receivers. To minimize static power consumption, we exploit dynamic comparators with built-in digitally tunable thresholds. The converter has been realized and tested outperforming recent comparable designs even in more advanced technologies. The main performance figures include 5.8GHz effective resolution bandwidth and 0.8pJ/conversion-step at 1-GS/s and Nyquist conditions

A 10.6mW/0.8pJ power-scalable 1GS/s 4b ADC in 0.18 um CMOS with 5.8GHz ERBW

TERRENI, PIERANGELO
2006

Abstract

We present a 4-bit power scalable flash analog-to-digital converter in digital 0.18-mum CMOS, targeting low power ultra-wide band receivers. To minimize static power consumption, we exploit dynamic comparators with built-in digitally tunable thresholds. The converter has been realized and tested outperforming recent comparable designs even in more advanced technologies. The main performance figures include 5.8GHz effective resolution bandwidth and 0.8pJ/conversion-step at 1-GS/s and Nyquist conditions
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11568/106160
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