In this paper we propose a new robust latch, referred to as HiPeR latch. It is insensitive to TFs affecting its internal and output nodes by design (independently of the size of its transistors), thus being scalable with technology node. It presents better or comparable robustness to TFs compared to the most recent latches in literature, while providing better characteristics in terms of performance at comparable area and power cost. © 2009 IEEE.
Novel high speed robust latch
Rossi D.
;
2009-01-01
Abstract
In this paper we propose a new robust latch, referred to as HiPeR latch. It is insensitive to TFs affecting its internal and output nodes by design (independently of the size of its transistors), thus being scalable with technology node. It presents better or comparable robustness to TFs compared to the most recent latches in literature, while providing better characteristics in terms of performance at comparable area and power cost. © 2009 IEEE.File in questo prodotto:
Non ci sono file associati a questo prodotto.
I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
