ROSSI, DANIELE Statistiche
ROSSI, DANIELE
DIPARTIMENTO DI INGEGNERIA DELL'INFORMAZIONE
A model for transient fault propagation in combinatorial logic
2003-01-01 Omana, M.; Papasso, G.; Rossi, D.; Metra, C.
A New Error Correcting Coding Technique to Tolerate Soft Errors
2021-01-01 Sen, Priyabrota; Sheikh Sadi, Muhammad; Ashab, Nabil; Rossi, Daniele
A novel dual-walled CNT bus architecture with reduced cross-coupling features
2006-01-01 Rossi, D.; Cazeaux, J. M.; Metra, C.; Lombardi, F.
A Support Vector Regression based Machine Learning method for on-chip Aging Estimation
2021-01-01 Alnuayri, Turki; Leonel Hernández Martínez, A.; Khursheed, Saqib; Rossi, Daniele
Accurate linear model for SET critical charge estimation
2009-01-01 Rossi, D.; Cazeaux, J. M.; Omana, M.; Metra, C.; Chatterjee, A.
Aging Benefits in Nanometer CMOS Designs
2017-01-01 Rossi, D.; Tenentes, V.; Yang, S.; Khursheed, S.; Al-Hashimi, B. M.
Analysis of BTI aging of level shifters
2016-01-01 Cai, J.; Halak, B.; Rossi, D.
Analysis of the impact of bus implemented EDCs on on-chip SSN
2006-01-01 Rossi, D.; Steiner, C.; Metra, C.
Analysis on Retention Time and Adaptive Refresh in Embedded DRAMs with Aging Benefits
2019-01-01 Najdi, A.; Rossi, D.; Tenentes, V.
BTI and leakage aware dynamic voltage scaling for reliable low power cache memories
2015-01-01 Rossi, D.; Tenentes, V.; Khursheed, S.; Al-Hashimi, B. M.
BTI aware thermal management for reliable DVFS designs
2016-01-01 Chahal, H.; Tenentes, V.; Rossi, D.; Al-Hashimi, B. M.
Can clock faults be detected through functional test?
2006-01-01 Metra, C.; Rossi, D.; Omana, M.; Cazeaux, J. M.; Mak, T. M.
Checker no-harm alarm robustness
2006-01-01 Rossi, D.; Omaña, M.; Metra, C.; Pagni, A.
Checkers' no-harm alarms and design approaches to tolerate Them
2018-01-01 Rossi, D.; Omana, M.; Metra, C.
Clock calibration faults and their impact on quality of high performance microprocessors
2003-01-01 Metra, C.; Mak, T. M.; Rossi, D.
Clock faults induced min and max delay violations
2014-01-01 Rossi, D.; Omana, M.; Cazeaux, J. M.; Metra, C.; Mak, T. M.
Coarse-Grained Online Monitoring of BTI Aging by Reusing Power-Gating Infrastructure
2017-01-01 Tenentes, V.; Rossi, D.; Yang, S.; Khursheed, S.; Al-Hashimi, B. M.; Gunn, S. R.
Coding scheme for low energy consumption fault-tolerant bus
2002-01-01 Rossi, D.; Van Dijk, V. E. S.; Kleihorst, R. P.; Nieuwland, A. H.; Metra, C.
Coding techniques for low switching noise in fault tolerant busses
2005-01-01 Nieuwland, A. K.; Katoch, A.; Rossi, D.; Metra, C.
Collective-Aware System-on-Chips for Dependable IoT Applications
2018-01-01 Tenentes, V.; Rossi, D.; Al-Hashimi, B. M.
| Titolo | Data di pubblicazione | Autore(i) | File |
|---|---|---|---|
| A model for transient fault propagation in combinatorial logic | 1-gen-2003 | Omana, M.; Papasso, G.; Rossi, D.; Metra, C. | |
| A New Error Correcting Coding Technique to Tolerate Soft Errors | 1-gen-2021 | Sen, Priyabrota; Sheikh Sadi, Muhammad; Ashab, Nabil; Rossi, Daniele | |
| A novel dual-walled CNT bus architecture with reduced cross-coupling features | 1-gen-2006 | Rossi, D.; Cazeaux, J. M.; Metra, C.; Lombardi, F. | |
| A Support Vector Regression based Machine Learning method for on-chip Aging Estimation | 1-gen-2021 | Alnuayri, Turki; Leonel Hernández Martínez, A.; Khursheed, Saqib; Rossi, Daniele | |
| Accurate linear model for SET critical charge estimation | 1-gen-2009 | Rossi, D.; Cazeaux, J. M.; Omana, M.; Metra, C.; Chatterjee, A. | |
| Aging Benefits in Nanometer CMOS Designs | 1-gen-2017 | Rossi, D.; Tenentes, V.; Yang, S.; Khursheed, S.; Al-Hashimi, B. M. | |
| Analysis of BTI aging of level shifters | 1-gen-2016 | Cai, J.; Halak, B.; Rossi, D. | |
| Analysis of the impact of bus implemented EDCs on on-chip SSN | 1-gen-2006 | Rossi, D.; Steiner, C.; Metra, C. | |
| Analysis on Retention Time and Adaptive Refresh in Embedded DRAMs with Aging Benefits | 1-gen-2019 | Najdi, A.; Rossi, D.; Tenentes, V. | |
| BTI and leakage aware dynamic voltage scaling for reliable low power cache memories | 1-gen-2015 | Rossi, D.; Tenentes, V.; Khursheed, S.; Al-Hashimi, B. M. | |
| BTI aware thermal management for reliable DVFS designs | 1-gen-2016 | Chahal, H.; Tenentes, V.; Rossi, D.; Al-Hashimi, B. M. | |
| Can clock faults be detected through functional test? | 1-gen-2006 | Metra, C.; Rossi, D.; Omana, M.; Cazeaux, J. M.; Mak, T. M. | |
| Checker no-harm alarm robustness | 1-gen-2006 | Rossi, D.; Omaña, M.; Metra, C.; Pagni, A. | |
| Checkers' no-harm alarms and design approaches to tolerate Them | 1-gen-2018 | Rossi, D.; Omana, M.; Metra, C. | |
| Clock calibration faults and their impact on quality of high performance microprocessors | 1-gen-2003 | Metra, C.; Mak, T. M.; Rossi, D. | |
| Clock faults induced min and max delay violations | 1-gen-2014 | Rossi, D.; Omana, M.; Cazeaux, J. M.; Metra, C.; Mak, T. M. | |
| Coarse-Grained Online Monitoring of BTI Aging by Reusing Power-Gating Infrastructure | 1-gen-2017 | Tenentes, V.; Rossi, D.; Yang, S.; Khursheed, S.; Al-Hashimi, B. M.; Gunn, S. R. | |
| Coding scheme for low energy consumption fault-tolerant bus | 1-gen-2002 | Rossi, D.; Van Dijk, V. E. S.; Kleihorst, R. P.; Nieuwland, A. H.; Metra, C. | |
| Coding techniques for low switching noise in fault tolerant busses | 1-gen-2005 | Nieuwland, A. K.; Katoch, A.; Rossi, D.; Metra, C. | |
| Collective-Aware System-on-Chips for Dependable IoT Applications | 1-gen-2018 | Tenentes, V.; Rossi, D.; Al-Hashimi, B. M. |