Scalable and reconfigurable VLSI architectures for low power and computation intensive signal processing

As electronic circuits enter the domain of silicon nanoscale technology the usual design space adopted in early years for solutions such as ASICs (Applied Specific Integrated Circuits), DSP (Digital Signal Processors) or GPP (General Purpose Processors) becomes inadequate. The possibility to integrate billions of transistors in single dies requires system designs providing efficient flexibility and scalability beyond the usual computing performance. New electronic paradigms are needed to fit reasonably all the implications and benefits of transistor geometries scaling down, both in terms of computing and communication infrastructure. In this work we prove that new computing solutions, such as ASIPs (Application Specific Instruction-set Processors), can offer an ideal compromise to dedicated computing solutions thanks to a much better trade off between performance and flexibility. Both static and dynamic configurable ASIP architectures are presented with reference to real case studies: The real-time and low-power implementation of computation intensive video coding and image processing algorithmic classes. To increase the computational power a large number of processing cores can be integrated in a single chip resulting in an MPSoC (Multi Processors System-on-Chip). Communication infrastructures become of vital importance to handle the design of such systems and NoC (Network on Chip) is the foreseen solution for a wide range of communication schemes required by applications. The most plausible scenario for future electronic systems exploiting complex functionality and large scale computation models is a SoC paradigm built upon NoC and reconfigurable ASIP solutions.