The authors describe a VLSI processor for pattern recognition based on content addressable memory (CAM) architecture, optimized for on-line track finding in high-energy physics experiments. A large CAM bank stores all trajectories of interest and extracts the ones compatible with a given event. This task is naturally parallelized by a CAM architecture able to output identified trajectories, searching for matches on 96-bit wide patterns, in just a few 40-MHz clock cycles. We have developed this device (called the AMchip03 processor) for the silicon vertex trigger (SVT) upgrade at the Collider Detector experiment at Fermilab (CDF) using a standard-cell VLSI design methodology. This approach provides excellent pattern density; while sparing many of the complexities and risks associated to a full-custom design. The cost/performance ratio is better by well more than one order of magnitude than an FPGA-based design. This processor has a flexible and easily configurable structure that makes it suitable for applications in other experimental environments. They look forward to sharing this technology.
|Autori:||Annovi A; Bardi A; Bitossi M; Chiozzi S; Damiani C; Dell'Orso M; Giannetti P; Giovacchini P; Marchiori G; Pedron I; Piendibene M; Sartori L; Schifano F; Spinella F; Torre S; Tripiccione R|
|Titolo:||A VLSI processor for fast track finding based on content addressable memories|
|Anno del prodotto:||2006|
|Digital Object Identifier (DOI):||10.1109/TNS.2006.876052|
|Appare nelle tipologie:||1.1 Articolo in rivista|