Mixed device-circuit simulations of 6T/8T SRAM cells employing tunnel-FETs

The scaling of the supply voltage VDD is an effective way to reduce power dissipation in digital circuits. The ION/IOFF ratio in conventional MOSFETs is limited by the thermionic electron emission, corresponding to a minimum sub-threshold swing SSmin ~ 60 mV/dec. Novel device architectures based on different operating principles are therefore gaining interest in order to reduce the static power dissipation (lowering IOFF at the same VDD) or the dynamic power (reducing VDD for the same IOFF) without affecting the performance ( ION). In the tunnel-FETs (TFETs), the conduction mechanism is the band-to-band tunneling (Fig.1), enabling a sub-60 mV/dec region (Fig.2) as demonstrated by experiments [1]. Among the main issues that may limit the employment of TFETs in digital circuits, we recall the drain current (ID) unidirectionality and the low ION.