STRANGIO, SEBASTIANO Statistiche

STRANGIO, SEBASTIANO  

DIPARTIMENTO DI INGEGNERIA DELL'INFORMAZIONE  

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Risultati 1 - 20 di 39 (tempo di esecuzione: 0.034 secondi).
Titolo Data di pubblicazione Autore(i) File
A 0.05 mm2, 350 mV, 14 nW fully-integrated temperature sensor in 180-nm CMOS 1-gen-2021 Zambrano, B.; Garzon, E.; Strangio, S.; Crupi, F.; Lanuzza, M.
A 0.6V–1.8V Compact Temperature Sensor with 0.24 °C Resolution, ±1.4 °C Inaccuracy and 1.06 nJ per Conversion 1-gen-2022 Zambrano, B.; Garzon, E.; Strangio, S.; Iannaccone, G.; Lanuzza, M.
All-Analog Silicon Integration of Image Sensor and Neural Computing Engine for Image Classification 1-gen-2022 Zambrano, B.; Strangio, S.; Rizzo, T.; Garzon, E.; Lanuzza, M.; Iannaccone, G.
Analog Vector-Matrix Multiplier Based on Programmable Current Mirrors for Neural Network Integrated Circuits 1-gen-2020 Paliy, Maksym; Strangio, Sebastiano; Ruiu, Piero; Rizzo, Tommaso; Iannaccone, Giuseppe
Analysis of TFET based 6T SRAM cells implemented with state of the art silicon nanowires 1-gen-2014 Strangio, S.; Palestri, P.; Esseni, D.; Selmi, L.; Crupi, F.
Assessment of InAs/AlGaSb Tunnel-FET Virtual Technology Platform for Low-Power Digital Circuits 1-gen-2016 Strangio, S.; Palestri, P.; Lanuzza, M.; Crupi, F.; Esseni, D.; Selmi, L.
Assessment of Two-Dimensional Materials-based technology for Analog Neural Networks 1-gen-2021 Paliy, Maksym; Strangio, Sebastiano; Ruiu, Piero; Iannaccone, Giuseppe
Benchmarks of a III-V TFET technology platform against the 10-nm CMOS FinFET technology node considering basic arithmetic circuits 1-gen-2017 Strangio, S.; Palestri, P.; Lanuzza, M.; Esseni, D.; Crupi, F.; Selmi, L.
Benchmarks of a III-V TFET technology platform against the 10-nm CMOS technology node considering 28T Full-Adders 1-gen-2016 Strangio, S.; Palestri, P.; Lanuzza, M.; Esseni, D.; Crupi, F.; Selmi, L.
Design of Ultra-Low Voltage/Power Circuits and Systems 1-gen-2022 Lanuzza, M.; De Rose, R.; Strangio, S.
Digital and analog TFET circuits: Design and benchmark 1-gen-2018 Strangio, S.; Settino, F.; Palestri, P.; Lanuzza, M.; Crupi, F.; Esseni, D.; Selmi, L.
Early assessment of tunnel-FET for energy-efficient logic circuits 1-gen-2017 Crupi, F.; Strangio, S.; Palestri, P.; Lanuzza, M.; Esseni, D.
Experimental characterization of the static noise margins of strained silicon complementary tunnel-FET SRAM 1-gen-2017 Luong, G. V.; Strangio, S.; Tiedemann, A. T.; Bernardy, P.; Trellenkamp, S.; Palestri, P.; Mantl, S.; Zhao, Q. T.
Experimental demonstration of strained Si nanowire GAA n-TFETs and inverter operation with complementary TFET logic at low supply voltages 1-gen-2016 Luong, G. V.; Strangio, S.; Tiedemannn, A.; Lenk, S.; Trellenkamp, S.; Bourdelle, K. K.; Zhao, Q. T.; Mantl, S.
Experimental examination of tunneling paths in SiGe/Si gate-normal tunneling field-effect transistors 1-gen-2017 Glass, S.; Von Den Driesch, N.; Strangio, S.; Schulte-Braucks, C.; Rieger, T.; Narimani, K.; Buca, D.; Mantl, S.; Zhao, Q. T.
Impact of TFET unidirectionality and ambipolarity on the performance of 6T SRAM cells 1-gen-2015 Strangio, S.; Palestri, P.; Esseni, D.; Selmi, L.; Crupi, F.; Richter, S.; Zhao, Q. -T.; Mantl, S.
Investigation of TFETs with Vertical Tunneling Path for Low Average Subthreshold Swing 1-gen-2017 Glass, S.; von den Driesch, N.; Strangio, Sebastiano; Schulte-Braucks, C.; Rieger, T.; Buca, D.; Mantl, S.; Zhao, Q. T.
Low frequency noise and gate bias instability in normally off AlGaN/GaN HEMTs 1-gen-2016 Crupi, F.; Magnone, P.; Strangio, S.; Iucolano, F.; Meneghesso, G.
Low-Power Artificial Neural Network Perceptron Based on Monolayer MoS2 1-gen-2022 Migliato Marega, G.; Wang, Z.; Paliy, M.; Giusi, G.; Strangio, S.; Castiglione, F.; Callegari, C.; Tripathi, M.; Radenovic, A.; Iannaccone, G.; Kis, A.
A Low-Voltage, Low-Power Reconfigurable Current-Mode Softmax Circuit for Analog Neural Networks 1-gen-2021 Vatalaro, M.; Moposita, T.; Strangio, S.; Trojman, L.; Vladimirescu, A.; Lanuzza, M.; Crupi, F.