A New Error Correcting Coding Technique to Tolerate Soft Errors

Multiple Cell Upsets (MCUs) are becoming a serious threat to memory reliability. Different types of Error-Correcting Codes (ECCs) are mostly used to protect memory against MCUs. However, there are some important issues often preventing many ECCs to be operating efficiently. Indeed, current ECCs for multiple errors require a time-consuming encoding/decoding process and exhibit a very high overhead. In this paper, a new coding technique is proposed to improve memory reliability featuring lower processing time and information overhead. It is based on the enhancement of the Decimal Matrix Code (DMC) in order to increase its error detection and correction ability yet featuring a lower redundancy compared to standard DMC. The performed simulations show that the proposed coding technique outperforms several existing ECC as far as error detection/correction ability is concerned. The proposed coding technique performs better than the DMC technique for more erroneous bits, e.g., more than three erroneous bits, as well as it has reduced redundant bits with respect to DMC.