Novel Transient Fault Hardened Static Latch

In this paper we analyze the effects of transient faults (TFs) affecting the internal nodes of conventional latch structures and we propose a new latch design which allows to tolerate such faults. In particular, we show that standard latches using back-to-back inverters for their positive feedback are very susceptible to glitches on their internal nodes. We propose a new latch that is hardened with respect to transient faults on the internal nodes and that provides lower power-delay product than classical implementations and alternate hardened solutions, while featuring a comparable or lower area overhead.