Impact of ECCs on simultaneously switching output noise for on-chip busses of high reliability systems

In this paper we analyze the impact of error correcting codes (ECCs) on simultaneously switching outputs (SSO) noise, for the case of a realistic bus of a high reliability system. First we analyze the effect of different bus transitions on SSO noise. Then we show how different ECCs, requiring a different number of check bits, impact the SSO noise. We prove that Hamming codes cause less noise than the ECCs that have been proposed so far to reduce power consumption and crosstalk-induced delay. In particular, we show that the code requirements for crosstalk and power minimization in terms of switching activity of adjacent wires are opposite to those for SSO noise reduction. Our analysis has been performed considering realistic bus and power supply network models, both implemented using a standard 0.25 μm CMOS technology.