This article proposes a method to design and implement an FPGA-based hardware accelerator for Convolutional Neural Networks (CNNs) exploiting Partial Reconfigurability (PR). The design strategy was applied to the CloudScout CNN case study, a network developed in the frame of the Φ -sat-1 ESA mission to perform cloud-detection aboard the satellite. The presented design based on Partial Reconfigurability was implemented, validated and characterized on a Xilinx ZCU106 Evaluation Board. The system was then compared with an alternative FPGA implementation reported in the literature to evaluate the obtained results. The comparison shows that the PR-based approach allows decreasing the resource utilization of the architecture, thus improving the network portability on smaller size FPGAs.
Design and Implementation of an FPGA-Based CNN Hardware Accelerator Using Partial Reconfigurability: The CloudScout Case Study
Pacini T.;Rapuano E.;Fanucci L.
2022-01-01
Abstract
This article proposes a method to design and implement an FPGA-based hardware accelerator for Convolutional Neural Networks (CNNs) exploiting Partial Reconfigurability (PR). The design strategy was applied to the CloudScout CNN case study, a network developed in the frame of the Φ -sat-1 ESA mission to perform cloud-detection aboard the satellite. The presented design based on Partial Reconfigurability was implemented, validated and characterized on a Xilinx ZCU106 Evaluation Board. The system was then compared with an alternative FPGA implementation reported in the literature to evaluate the obtained results. The comparison shows that the PR-based approach allows decreasing the resource utilization of the architecture, thus improving the network portability on smaller size FPGAs.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
