In this work we create an environment to validate and implement a GPS L1 C/A fast acquisition core on COTS FPGAs. The frequency domain PCPS algorithm is studied on a Scilab test bench and the results are compared with the outputs of the GNSS-SDR simulator. Then all the PCPS algorithmic blocks are designed and fitted on an FPGA. The hardware core is successfully used to acquire GPS L1 C/A signal records. Timing and area results are analyzed to understand how to extend the design to modern GPS signals.
Exploring GPS L1 C/A Fast Acquisition with COTS FPGA
Fanucci L.
2022-01-01
Abstract
In this work we create an environment to validate and implement a GPS L1 C/A fast acquisition core on COTS FPGAs. The frequency domain PCPS algorithm is studied on a Scilab test bench and the results are compared with the outputs of the GNSS-SDR simulator. Then all the PCPS algorithmic blocks are designed and fitted on an FPGA. The hardware core is successfully used to acquire GPS L1 C/A signal records. Timing and area results are analyzed to understand how to extend the design to modern GPS signals.File in questo prodotto:
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