An excessive sensitivity to PVT variations may represent a considerable issue of a Current Reference (CR) circuit, possibly resulting in poor reliability of CR-supplied systems. CR area occupation is also critical in size-constrained designs. In this work, we present and analyze a compact all-MOSFETs CR topology. Implemented in 0.18 μm CMOS, the proposed design generates a 946 nA reference current. Simulated temperature coefficient and line sensitivity are equal to 318 ppm/°C and 5.12%/V, respectively. Besides, based on process sensitivity analyses, the reference current exhibited a relative standard deviation equal to 0.88%, which is competitive with state-of-the-art solutions.

A Compact All-MOSFETs PVT-compensated Current Reference with Untrimmed 0.88%-(σ/μ)

Gagliardi F.
Primo
;
Catania A.
Secondo
;
Ria A.;Bruschi P.
Penultimo
;
Piotto M.
Ultimo
2023-01-01

Abstract

An excessive sensitivity to PVT variations may represent a considerable issue of a Current Reference (CR) circuit, possibly resulting in poor reliability of CR-supplied systems. CR area occupation is also critical in size-constrained designs. In this work, we present and analyze a compact all-MOSFETs CR topology. Implemented in 0.18 μm CMOS, the proposed design generates a 946 nA reference current. Simulated temperature coefficient and line sensitivity are equal to 318 ppm/°C and 5.12%/V, respectively. Besides, based on process sensitivity analyses, the reference current exhibited a relative standard deviation equal to 0.88%, which is competitive with state-of-the-art solutions.
2023
979-8-3503-0320-9
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11568/1207569
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