This work presents the design and synthesis of a processing unit for numbers encoded according to the recently introduced BAN format. Such an encoding allows one to represent numbers which are not only finite (as the reals) but also infinitely large or infinitely small, i.e., non-Archimedean. The motivation behind this study is the significant burst the non-Archimedean numerical computations have received in the last 20 years and the applications that have been found. With a hardware support, this operations would significantly increase in speed, enlarging the spectrum of possible applications to industrial and real-time ones.
Design and FPGA Synthesis of BAN Processing Unit for Non-Archimedean Number Crunching
Rossi F.;Fiaschi L.;Cococcioni M.;Saponara S.
2023-01-01
Abstract
This work presents the design and synthesis of a processing unit for numbers encoded according to the recently introduced BAN format. Such an encoding allows one to represent numbers which are not only finite (as the reals) but also infinitely large or infinitely small, i.e., non-Archimedean. The motivation behind this study is the significant burst the non-Archimedean numerical computations have received in the last 20 years and the applications that have been found. With a hardware support, this operations would significantly increase in speed, enlarging the spectrum of possible applications to industrial and real-time ones.File in questo prodotto:
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