This paper presents a new family of Class-AB operational transconductance amplifier (OTA) circuits based on single-stage topologies with non-linear current amplifiers. The proposed variable-mirror amplifier (VMA) architecture is mainly characterized by generating all Class-AB current in the output transistors only, by exhibiting very low sensitivity to both technology and temperature deviations, and by avoiding the need for any internal frequency-compensation mechanism. Hence, this family of OTAs is well-suited for low-power switched-capacitor circuits and specifically optimized for switched-OpAmp fast on-off operation and multi-decade load-capacitance specifications. Analytical expressions valid in all regions of operation are presented to minimize VMA settling time in discrete-time circuits. Also, a complete OTA design example integrated in 0.18 μ 1P6M MiM 1.8 V CMOS technology is supplied with detailed simulation and experimental results. Compared to resistor-free state-of-art Class-AB OpAmp and OTA literature, the proposed architecture returns the highest measured figure-of-merit value.
Variable-Mirror Amplifier: A New Family of Process-Independent Class-AB Single-Stage OTAs for Low-Power SC Circuits
Dei M.Secondo
;
2016-01-01
Abstract
This paper presents a new family of Class-AB operational transconductance amplifier (OTA) circuits based on single-stage topologies with non-linear current amplifiers. The proposed variable-mirror amplifier (VMA) architecture is mainly characterized by generating all Class-AB current in the output transistors only, by exhibiting very low sensitivity to both technology and temperature deviations, and by avoiding the need for any internal frequency-compensation mechanism. Hence, this family of OTAs is well-suited for low-power switched-capacitor circuits and specifically optimized for switched-OpAmp fast on-off operation and multi-decade load-capacitance specifications. Analytical expressions valid in all regions of operation are presented to minimize VMA settling time in discrete-time circuits. Also, a complete OTA design example integrated in 0.18 μ 1P6M MiM 1.8 V CMOS technology is supplied with detailed simulation and experimental results. Compared to resistor-free state-of-art Class-AB OpAmp and OTA literature, the proposed architecture returns the highest measured figure-of-merit value.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
