Design and~Implementation on~{FPGA} of~a~{HW} Accelerator for~Post-Quantum {RLWE} Polynomial Operations

Ring learning with errors (RLWE) is largely adopted in Post-Quantum cryptography and Homomorphic encryption schemes. RLWE cryptosystems are defined over polynomial quotient rings, where polynomial additions/subtractions and multiplication are required. In this paper we propose the implementation of a hardware accelerator for polynomial operations required in RLWE cryptosystems. Such hardware accelerator includes a Arithmetic Logic Unit (ALU) able to perform polynomial additions/subtractions and multiplications. The latter adopts Negative Wrapped Convolution (NWC) and Number Theoretic Transform (NTT) techniques. The hardware accelerator has been integrated in a hardware system for accelerating the NewHope-1024 algorithm, and a demo on a Intel DE4 FPGA board has been developed to test the functionality of the system. Synthesis results on different FPGA technologies are proposed too, showing competitive performances respect to the State of Art.