DI MATTEO, STEFANO Statistiche
DI MATTEO, STEFANO
DIPARTIMENTO DI INGEGNERIA DELL'INFORMAZIONE
A PUF-Based Secure Boot for RISC-V Architectures
2024-01-01 DI MATTEO, Stefano; Zulberti, Luca; Cosimo Lapenna, Federico; Nannipieri, Pietro; Crocetti, Luca; Fanucci, Luca; Saponara, Sergio
CRYPHTOR: A Memory-Unified NTT-Based Hardware Accelerator for Post-Quantum CRYSTALS Algorithms
2024-01-01 Di Matteo, Stefano; Sarno, Ivan; Saponara, Sergio
Cycle-Accurate Verification of the Cryptographic Co-Processor for the European Processor Initiative
2024-01-01 Nannipieri, Pietro; DI MATTEO, Stefano; Crocetti, Luca; Zulberti, Luca; Fanucci, Luca; Saponara, Sergio
HW-SW Interface Design and Implementation for Error Logging and Reporting for RAS Improvement
2024-01-01 Canino, Nicasio; DI MATTEO, Stefano; Rossi, Daniele; Saponara, Sergio
On hardware acceleration of quantum-resistant FOTA systems in automotive
2024-01-01 Perazzo, Pericle; Di Matteo, Stefano; Dini, Gianluca; Saponara, Sergio
RTL Flow for the Power Side-Channel Resilience Assessment of a Post-quantum SHA-3 Accelerator
2024-01-01 Tenentes, Vasileios; DI MATTEO, Stefano; Zonios, Christos; Rossi, Daniele; Saponara, Sergio
Design and Evaluation of a Peripheral for Integrity Checking to Improve RAS in RISC-V Architectures
2023-01-01 Rossi, Daniele; Canino, Nicasio; DI MATTEO, Stefano; Saponara, Sergio; Tenentes, Vasileios
Design Methodology and Metrics for Robust and Highly Qualified Security Modules in Trusted Environments
2023-01-01 Crocetti, Luca; Nannipieri, Pietro; Di Matteo, Stefano; Saponara, Sergio
Hardware Design of an Advanced-Feature Cryptographic Tile within the European Processor Initiative
2023-01-01 Nannipieri, Pietro; Crocetti, Luca; Di Matteo, Stefano; Fanucci, Luca; Saponara, Sergio
Innovative Plug-and-Play System for Electrification of Wheel-Chairs
2023-01-01 Pacini, F.; Di Matteo, S.; Dini, P.; Fanucci, L.; Bucchi, F.
Review of Methodologies and Metrics for Assessing the Quality of Random Number Generators
2023-01-01 Crocetti, L; Nannipieri, P; Di Matteo, S; Fanucci, L; Saponara, S
VLSI Design and FPGA Implementation of an NTT Hardware Accelerator for Homomorphic SEAL-Embedded Library
2023-01-01 Di Matteo, S; Lo Gerfo, M; Saponara, S
A Script-Based Cycle-True Verification Framework to Speed-Up Hardware and Software Co-Design: Performance Evaluation on ECC Accelerator Use-Case
2022-01-01 Zulberti, Luca; DI MATTEO, Stefano; Nannipieri, Pietro; Saponara, Sergio; Fanucci, Luca
CRFlex: A Flexible and Configurable Cryptographic Hardware Accelerator for AES Block Cipher Modes
2022-01-01 Nannipieri, P.; Baldanzi, L.; Crocetti, L.; Di Matteo, S.; Falaschi, F.; Fanucci, L.; Saponara, S.
Design and Test of an Integrated Random Number Generator with All-Digital Entropy Source
2022-01-01 Crocetti, L.; Di Matteo, S.; Nannipieri, P.; Fanucci, L.; Saponara, S.
Dispositivo di motorizzazione per sedia a rotelle
2022-01-01 Bucchi, Francesco; Pucci, Francesco; Pacini, Federico; Nardini, Paolo; Mondini, Dario; Frendo, Francesco; Fanucci, Luca; Dini, Pierpaolo; DI MATTEO, Stefano
VLSI Design of Advanced-Features AES Cryptoprocessor in the Framework of the European Processor Initiative
2022-01-01 Nannipieri, P.; Matteo, S. D.; Baldanzi, L.; Crocetti, L.; Zulberti, L.; Saponara, S.; Fanucci, L.
A RISC-V Post Quantum Cryptography Instruction Set Extension for Number Theoretic Transform to Speed-Up CRYSTALS Algorithms
2021-01-01 Nannipieri, P.; Di Matteo, S.; Zulberti, L.; Albicocchi, F.; Saponara, S.; Fanucci, L.
Secure elliptic curve crypto-processor for real-time iot applications
2021-01-01 Di Matteo, S.; Baldanzi, L.; Crocetti, L.; Nannipieri, P.; Fanucci, L.; Saponara, S.
SHA2 and SHA-3 accelerator design in a 7 nm technology within the European Processor Initiative
2021-01-01 Nannipieri, P.; Bertolucci, M.; Baldanzi, L.; Crocetti, L.; Di Matteo, S.; Falaschi, F.; Fanucci, L.; Saponara, S.
| Titolo | Data di pubblicazione | Autore(i) | File |
|---|---|---|---|
| A PUF-Based Secure Boot for RISC-V Architectures | 1-gen-2024 | DI MATTEO, Stefano; Zulberti, Luca; Cosimo Lapenna, Federico; Nannipieri, Pietro; Crocetti, Luca; Fanucci, Luca; Saponara, Sergio | |
| CRYPHTOR: A Memory-Unified NTT-Based Hardware Accelerator for Post-Quantum CRYSTALS Algorithms | 1-gen-2024 | Di Matteo, Stefano; Sarno, Ivan; Saponara, Sergio | |
| Cycle-Accurate Verification of the Cryptographic Co-Processor for the European Processor Initiative | 1-gen-2024 | Nannipieri, Pietro; DI MATTEO, Stefano; Crocetti, Luca; Zulberti, Luca; Fanucci, Luca; Saponara, Sergio | |
| HW-SW Interface Design and Implementation for Error Logging and Reporting for RAS Improvement | 1-gen-2024 | Canino, Nicasio; DI MATTEO, Stefano; Rossi, Daniele; Saponara, Sergio | |
| On hardware acceleration of quantum-resistant FOTA systems in automotive | 1-gen-2024 | Perazzo, Pericle; Di Matteo, Stefano; Dini, Gianluca; Saponara, Sergio | |
| RTL Flow for the Power Side-Channel Resilience Assessment of a Post-quantum SHA-3 Accelerator | 1-gen-2024 | Tenentes, Vasileios; DI MATTEO, Stefano; Zonios, Christos; Rossi, Daniele; Saponara, Sergio | |
| Design and Evaluation of a Peripheral for Integrity Checking to Improve RAS in RISC-V Architectures | 1-gen-2023 | Rossi, Daniele; Canino, Nicasio; DI MATTEO, Stefano; Saponara, Sergio; Tenentes, Vasileios | |
| Design Methodology and Metrics for Robust and Highly Qualified Security Modules in Trusted Environments | 1-gen-2023 | Crocetti, Luca; Nannipieri, Pietro; Di Matteo, Stefano; Saponara, Sergio | |
| Hardware Design of an Advanced-Feature Cryptographic Tile within the European Processor Initiative | 1-gen-2023 | Nannipieri, Pietro; Crocetti, Luca; Di Matteo, Stefano; Fanucci, Luca; Saponara, Sergio | |
| Innovative Plug-and-Play System for Electrification of Wheel-Chairs | 1-gen-2023 | Pacini, F.; Di Matteo, S.; Dini, P.; Fanucci, L.; Bucchi, F. | |
| Review of Methodologies and Metrics for Assessing the Quality of Random Number Generators | 1-gen-2023 | Crocetti, L; Nannipieri, P; Di Matteo, S; Fanucci, L; Saponara, S | |
| VLSI Design and FPGA Implementation of an NTT Hardware Accelerator for Homomorphic SEAL-Embedded Library | 1-gen-2023 | Di Matteo, S; Lo Gerfo, M; Saponara, S | |
| A Script-Based Cycle-True Verification Framework to Speed-Up Hardware and Software Co-Design: Performance Evaluation on ECC Accelerator Use-Case | 1-gen-2022 | Zulberti, Luca; DI MATTEO, Stefano; Nannipieri, Pietro; Saponara, Sergio; Fanucci, Luca | |
| CRFlex: A Flexible and Configurable Cryptographic Hardware Accelerator for AES Block Cipher Modes | 1-gen-2022 | Nannipieri, P.; Baldanzi, L.; Crocetti, L.; Di Matteo, S.; Falaschi, F.; Fanucci, L.; Saponara, S. | |
| Design and Test of an Integrated Random Number Generator with All-Digital Entropy Source | 1-gen-2022 | Crocetti, L.; Di Matteo, S.; Nannipieri, P.; Fanucci, L.; Saponara, S. | |
| Dispositivo di motorizzazione per sedia a rotelle | 1-gen-2022 | Bucchi, Francesco; Pucci, Francesco; Pacini, Federico; Nardini, Paolo; Mondini, Dario; Frendo, Francesco; Fanucci, Luca; Dini, Pierpaolo; DI MATTEO, Stefano | |
| VLSI Design of Advanced-Features AES Cryptoprocessor in the Framework of the European Processor Initiative | 1-gen-2022 | Nannipieri, P.; Matteo, S. D.; Baldanzi, L.; Crocetti, L.; Zulberti, L.; Saponara, S.; Fanucci, L. | |
| A RISC-V Post Quantum Cryptography Instruction Set Extension for Number Theoretic Transform to Speed-Up CRYSTALS Algorithms | 1-gen-2021 | Nannipieri, P.; Di Matteo, S.; Zulberti, L.; Albicocchi, F.; Saponara, S.; Fanucci, L. | |
| Secure elliptic curve crypto-processor for real-time iot applications | 1-gen-2021 | Di Matteo, S.; Baldanzi, L.; Crocetti, L.; Nannipieri, P.; Fanucci, L.; Saponara, S. | |
| SHA2 and SHA-3 accelerator design in a 7 nm technology within the European Processor Initiative | 1-gen-2021 | Nannipieri, P.; Bertolucci, M.; Baldanzi, L.; Crocetti, L.; Di Matteo, S.; Falaschi, F.; Fanucci, L.; Saponara, S. |