A voltage controlled CMOS current divider with linear characteristic

A compact voltage controlled CMOS current divider is presented. Differently from previous implementations, exploiting the MOSFET translinear characteristics in subthreshold region, the proposed circuit is based on devices operating from moderate to strong inversion. An input current linearity range of nearly a decade is obtained by compensating for the deviations from the ideal drain current square-law approximation through an original empirical approach. The circuit is suitable for use as building block in analog multipliers and for transconductor continuous tuning. The effectiveness of the proposed configuration is demonstrated by means of electrical simulations, performed on a prototype designed with a commercial process. The robustness of the linearization algorithm with respect to temperature variations is proven.