Reducing the Energy Footprint of 5G: A gNB on MPSoC With Low-Power FFT Acceleration

Open, virtualized architectures are reshaping cellular networks, but purely software-based 5G deployments often struggle to meet strict real-time requirements. Thus, accelerators are often utilised even at the expense of a high energy consumption, in part due to the overhead introduced by host-to-device data transfers. In this paper, we propose and demonstrate an energy-efficient solution that accelerates Fast Fourier Transform computations by placing Low-PHY functions in an MPSoC FPGA. Moreover, by placing High-PHY layer functions in the CPU of the same MPSoC, we eliminate host-to-accelerator bottlenecks (e.g., accelerator to processor transfer time) that typically limit hardware speedups and contribute to unnecessary energy expenditure. Though implemented into a single MPSoC, the solution is compatible with Open RAN solutions, such as the one proposed by the Small Cell Forum in the 5G function application platform interface. Experimental results using OpenAirInterface demonstrate that the MPSoC-based approach achieves up to 13× speedup compared to CPU-based implementations, particularly for larger Fast Fourier Transform sizes, which directly contributes to reduced energy consumption per processed task. Furthermore, a detailed power consumption analysis shows that, while the processing system remains a significant energy consumer, hardware acceleration enhances overall energy efficiency by shifting computationally intensive tasks to dedicated hardware optimized for parallel, energy-efficient processing, substantially reducing their energy consumption and paving the way for greener 5G deployments.