RAS Enhancement of ECC-Protected Vector Register File for the RISC-V Architecture via RERI-Compliant Interface

High-performance computing (HPC) systems increasingly rely on vector architectures to provide the scalability and parallelism required for large-scale data processing. The RISC-V Vector Extension (RVV), defined within the open and modular RISC-V architecture, has emerged as a prominent standard in this domain. A central component of RVV-enabled processors is the vector register file (VRF), whose capacity scales with vector length and implementation parameters, thereby increasing its susceptibility to hardware faults, including transient soft errors and permanent aging-related failures. Because the VRF stores critical architectural state, inadequate protection may lead to silent data corruption, which is particularly detrimental in large HPC deployments. This work enhances system reliability, availability, and serviceability (RAS) by integrating Single-Error Correction and Double-Error Detection (SECDED) error-correcting codes within the VRF. In addition, we implement the RISC-V RAS Error Logging and Reporting Interface (RERI), which defines a unified error taxonomy and memory-mapped error records to report hardware events to the system software. Experimental results show that the combination of SECDED protection and a RERI-compliant hardware-software interface significantly improves the resilience (i.e. RAS) of RVV-based processors while incurring modest and implementation-tunable area overhead.