The Belle II experiment at the SuperKEKB storage ring in Japan plans an upgrade of its vertex detector to cope with the increasing luminosities up to 6 × 1035 cm-2 s-1. The proposed vertex detector (VTX) consists of 6 fully pixelated barrel-shaped layers amounting to a material budget of 3.5 %X 0 using the specifically developed OBELIX chip. It is a depleted monolithic active pixel sensor (DMAPS) in 180 nm CMOS technology. It is derived from the TJ-Monopix2 and inherits the matrix design, while the periphery was reworked for compatibility with the Belle II requirements. It features a 33 μm pixel pitch, time stamping with 50 ns resolution and supports trigger rates up to 30 kHz at a trigger delay of 10 μs. We present test beam results of irradiated chips in a temperature controlled environment to test the feasibility of operation in a temperature range of 10° C to 50° C and comparing the performance of the available front-ends under these conditions. The results will impact the thermal design and choice of front-end for the final design of OBELIX.
Upgrade of the Belle II vertex detector with depleted monolithic CMOS active pixel sensors
Benfratello G. F.;Bettarini S.;Bosi F.;Casarosa G.;Corona L.;Forti F.;Massaccesi L.;Minuti M.;Mondal S.;Rizzo G.;Taffara A.;Bevan A.;
2025-01-01
Abstract
The Belle II experiment at the SuperKEKB storage ring in Japan plans an upgrade of its vertex detector to cope with the increasing luminosities up to 6 × 1035 cm-2 s-1. The proposed vertex detector (VTX) consists of 6 fully pixelated barrel-shaped layers amounting to a material budget of 3.5 %X 0 using the specifically developed OBELIX chip. It is a depleted monolithic active pixel sensor (DMAPS) in 180 nm CMOS technology. It is derived from the TJ-Monopix2 and inherits the matrix design, while the periphery was reworked for compatibility with the Belle II requirements. It features a 33 μm pixel pitch, time stamping with 50 ns resolution and supports trigger rates up to 30 kHz at a trigger delay of 10 μs. We present test beam results of irradiated chips in a temperature controlled environment to test the feasibility of operation in a temperature range of 10° C to 50° C and comparing the performance of the available front-ends under these conditions. The results will impact the thermal design and choice of front-end for the final design of OBELIX.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
