The Silicon Vertex Trigger (SVT) at CDF is made of two pipelined processors: the Associative Memory finding low precision tracks and the Track Fitter refining the track quality with high-precision fits. We will describe the performance of a next generation track fitter, the GigaFitter, that performs more than a fit per nanosecond. It is going to be inserted parasitically in SVT to study its capabilities to improve data taking during the high luminosity CDF runs. This device is based on modem FPGA technology, rich of powerful DSP arrays, to reduce the track parameter reconstruction to few clock cycles and perform many fits in parallel. The goal of the design was to reduce significantly the processing time required for fitting and thus allow more time for the subsequent high resolution track-fitting. Preliminary results on the algorithm latency are presented. A future more power-full version of the GigaFitter intended for WC experiments is also discussed. (C) 2010 Elsevier B.V. All rights reserved.
|Autori interni:||DELL'ORSO, MAURO|
|Autori:||Amerio S; Annovi A; Basile M; Bettini M; Bucciantonio M; Catastini P; Cenni J; Crescioli F; Dell'Orso M; Giannetti P; Giuliani E; Lucchesi D; Nicoletto M; Piendibene M; Rafanelli N; Volpi G|
|Titolo:||GigaFitter: Performance at CDF and perspective for future applications|
|Anno del prodotto:||2010|
|Digital Object Identifier (DOI):||10.1016/j.nima.2010.03.063|
|Appare nelle tipologie:||1.1 Articolo in rivista|