An array of low-complex SAR ADCs, configurable in time-interleaved (TI) or parallel modes to reach 1 GS/s or to serve multiple inputs at hundreds of MS/s, is proposed in this letter. Each SAR ADC channel exploits a threshold-configuring scheme, to avoid internal DAC thus saving circuit complexity, plus a dynamic comparator which allows for power consumption scalable versus processing speed. Implementation results in 90 nm 1 V CMOS technology are presented and compared to the state of the art.
Configurable array of low-complex SAR ADCs
SAPONARA, SERGIO
2011-01-01
Abstract
An array of low-complex SAR ADCs, configurable in time-interleaved (TI) or parallel modes to reach 1 GS/s or to serve multiple inputs at hundreds of MS/s, is proposed in this letter. Each SAR ADC channel exploits a threshold-configuring scheme, to avoid internal DAC thus saving circuit complexity, plus a dynamic comparator which allows for power consumption scalable versus processing speed. Implementation results in 90 nm 1 V CMOS technology are presented and compared to the state of the art.File in questo prodotto:
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