A new two's complement serial multiplier based on a pipelined diagonal-wise interlaced structure is presented. Two N x M multiplications are processed simultaneously, which is particularly useful for a high-throughput area-efficient complex number multiplier. Using the proposed scheme, an 8 x 8 bit complex multiplier prototype was realised in 0.25 mum standard cell CMOS technology with 1.6 Kgates complexity for a maximum operating frequency of 550MHz.
|Autori:||Fanucci L; Forliti M|
|Titolo:||Interlaced diagonal-wise pipelined serial multiplier|
|Anno del prodotto:||2000|
|Digital Object Identifier (DOI):||10.1049/el:20001252|
|Appare nelle tipologie:||1.1 Articolo in rivista|