A new two's complement serial multiplier based on a pipelined diagonal-wise interlaced structure is presented. Two N x M multiplications are processed simultaneously, which is particularly useful for a high-throughput area-efficient complex number multiplier. Using the proposed scheme, an 8 x 8 bit complex multiplier prototype was realised in 0.25 mum standard cell CMOS technology with 1.6 Kgates complexity for a maximum operating frequency of 550MHz.

Interlaced diagonal-wise pipelined serial multiplier

FANUCCI, LUCA;
2000

Abstract

A new two's complement serial multiplier based on a pipelined diagonal-wise interlaced structure is presented. Two N x M multiplications are processed simultaneously, which is particularly useful for a high-throughput area-efficient complex number multiplier. Using the proposed scheme, an 8 x 8 bit complex multiplier prototype was realised in 0.25 mum standard cell CMOS technology with 1.6 Kgates complexity for a maximum operating frequency of 550MHz.
Fanucci, Luca; Forliti, M.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11568/160775
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