The problem of an efficient VLSI realization of the 2-D discrete-cosine-transform and its inverse is addressed in this paper. Two circuits implementing both functions are discussed and characterized from the high-level architectural choices down to the gate-level synthesis on different standard-cell target technologies. The circuits are designed as parametric intellectual property (IP) cells according to a design reuse policy that allows the user to select the most convenient solution for the considered application. Synthesis results show that the circuits are suitable for real time processing of various image formats adopted in H.263/MPEG compression standards. Power consumption reduction methods (clock gating, switching activity reduction) are used according to the statistics of the input signals to reduce the dissipated power. The effects of supply voltage scaling and its consequence on circuit performance are examined in detail, as well as the use of different target technologies. Finally, a comparison with dedicated full-custom low-power circuits presented in the literature show that these IP cells stand for flexibility, parametrization and reusability, still maintaining comparable power consumption and area occupation. (C) 2001 Elsevier Science Ltd. All rights reserved.
|Autori:||Fanucci L; Saletti R; Saponara S|
|Titolo:||Parametrized and reusable VLSI macro cells for the low-power realization of 2-D discrete-cosine-transform|
|Anno del prodotto:||2001|
|Digital Object Identifier (DOI):||10.1016/S0026-2692(01)00092-1|
|Appare nelle tipologie:||1.1 Articolo in rivista|