The Fanout system is part of the Silicon Vertex Tracker (SVT), a new trigger processor designed to reconstruct charged particle trajectories at level 2 (L2) of the CDF trigger, with a latency of 10 mus and an event rate up to 100 kHz. The core of SVT is organized as 12 identical slices, which process in parallel the data from the 12 independent azimuthal wedges of the Silicon Vertex Detector (SVXII). Each SVT slice links the digitized pulse heights found within one SVXII wedge to the tracks reconstructed by the level I (L1) fast track finder (XFT) in the corresponding 301 angular region of the Central Outer Tracker (COT). Since the XFT tracks are transmitted to SVT as a single data stream, their distribution to the proper SVT slices requires dedicated fanout logic. The fanout system has been implemented as a multiboard project running on a common 20-MHz clock. Track fanout is performed in two steps by one "Fanout A" and two "Fanout B" boards. The architecture, design, and implementation of this system are described.
A two-level Fanout system for the CDF Silicon Vertex Tracker
DELL'ORSO, MAURO;DONATI, SIMONE;PUNZI, GIOVANNI;
2001-01-01
Abstract
The Fanout system is part of the Silicon Vertex Tracker (SVT), a new trigger processor designed to reconstruct charged particle trajectories at level 2 (L2) of the CDF trigger, with a latency of 10 mus and an event rate up to 100 kHz. The core of SVT is organized as 12 identical slices, which process in parallel the data from the 12 independent azimuthal wedges of the Silicon Vertex Detector (SVXII). Each SVT slice links the digitized pulse heights found within one SVXII wedge to the tracks reconstructed by the level I (L1) fast track finder (XFT) in the corresponding 301 angular region of the Central Outer Tracker (COT). Since the XFT tracks are transmitted to SVT as a single data stream, their distribution to the proper SVT slices requires dedicated fanout logic. The fanout system has been implemented as a multiboard project running on a common 20-MHz clock. Track fanout is performed in two steps by one "Fanout A" and two "Fanout B" boards. The architecture, design, and implementation of this system are described.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
