In this paper, the design of a very large scale integration (VLSI) architecture for low-power H.263/MPEG-4 video codec is addressed. Starting from a high-level system modelling, a profiling analysis indicates a hardware-software (HW-SW) partitioning assuming power consumption. flexibility and circuit complexity as main cost functions. The architecture is based on a reduced instruction set computer engine, enhanced by dedicated hardware processing, with a memory hierarchy organisation and direct memory access-based data transfers. To reduce the system power consumption two main strategies have been adopted. The first consists in the design of a low-power high-efficiency motion estimator specifically targeted to low bit-rate applications. Exploiting the correlation of video motion field it attains the same high coding efficiency of the full-search approach for a computational burden lower than about two orders of magnitude. Combining the decreased algorithm complexity with low-power VLSI design techniques the motion estimator power consumption is scaled down to few mW. The second consists in the implementation of a proper buffer hierarchy to reduce memory and bus power consumption in the HW-SW communication. The effectiveness of the proposed architecture has been validated through performance measurements on a prototyping platform. (C) 2002 Elsevier Science Ltd. All rights reserved.
|Autori:||Chimienti A; Fanucci L; Locatelli R; Saponara S|
|Titolo:||VLSI architecture for a low-power video codec system|
|Anno del prodotto:||2002|
|Digital Object Identifier (DOI):||10.1016/S0026-2692(02)00009-5|
|Appare nelle tipologie:||1.1 Articolo in rivista|