A reduction of the non-linearity of a CMOS all-digital shunt-capacitor delay-line is achieved by performing an on-line statistical test of the line and correcting the individual cell delay mismatch according to the test results. A fully digital cell controller efficiently implementing the calibration procedure has been realized. Simulation results show the feasibility of the technique and the substantial reduction of the non-linearity down to values lower then 1%.
On-line calibration for non-linearity reduction of delay-locked delay-lines
BARONTI, FEDERICO;FANUCCI, LUCA;RONCELLA, ROBERTO;SALETTI, ROBERTO
2001-01-01
Abstract
A reduction of the non-linearity of a CMOS all-digital shunt-capacitor delay-line is achieved by performing an on-line statistical test of the line and correcting the individual cell delay mismatch according to the test results. A fully digital cell controller efficiently implementing the calibration procedure has been realized. Simulation results show the feasibility of the technique and the substantial reduction of the non-linearity down to values lower then 1%.File in questo prodotto:
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