This work studies the feasibility of a new implementation of CMOS monolithic active pixel sensors (MAPS) for applications to charged particle tracking. As compared to standard three MOSFET MAPS, where the charge signal is readout by a source follower, the proposed front-end scheme relies upon a charge sensitive amplifier (CSA), embedded in the elementary pixel cell, to perform charge-to-voltage conversion. The area required for the integration of the front-end electronics is mostly provided by the collecting electrode, which consists of a deep n-type diffusion, available as a shielding frame for n-channel devices in deep submicron, triple well CMOS technologies. Based on the above concept, a chip, which includes several test structures differing in the sensitive element area, has been fabricated in a 0.13 mu m CMOS process. In this paper, the criteria underlying the design of the pixel level analog processor will be presented, together with some preliminary experimental results demonstrating the feasibility of the proposed approach. (c) 2006 Elsevier B.V. All rights reserved.

Monolithic pixel detectors in a 0.13 mu m CMOS technology with sensor level continuous time charge amplification and shaping

BETTARINI, STEFANO;CALDERINI, GIOVANNI;GIORGI, MARCELLO;FORTI, FRANCESCO;RIZZO, GIULIANA
2006-01-01

Abstract

This work studies the feasibility of a new implementation of CMOS monolithic active pixel sensors (MAPS) for applications to charged particle tracking. As compared to standard three MOSFET MAPS, where the charge signal is readout by a source follower, the proposed front-end scheme relies upon a charge sensitive amplifier (CSA), embedded in the elementary pixel cell, to perform charge-to-voltage conversion. The area required for the integration of the front-end electronics is mostly provided by the collecting electrode, which consists of a deep n-type diffusion, available as a shielding frame for n-channel devices in deep submicron, triple well CMOS technologies. Based on the above concept, a chip, which includes several test structures differing in the sensitive element area, has been fabricated in a 0.13 mu m CMOS process. In this paper, the criteria underlying the design of the pixel level analog processor will be presented, together with some preliminary experimental results demonstrating the feasibility of the proposed approach. (c) 2006 Elsevier B.V. All rights reserved.
2006
Ratti, L; Manghisoni, M; Re, V; Speziali, V; Traversi, G; Bettarini, Stefano; Calderini, Giovanni; Cenci, R; Giorgi, Marcello; Forti, Francesco; Morsa...espandi
File in questo prodotto:
Non ci sono file associati a questo prodotto.

I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.

Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11568/180936
 Attenzione

Attenzione! I dati visualizzati non sono stati sottoposti a validazione da parte dell'ateneo

Citazioni
  • ???jsp.display-item.citation.pmc??? ND
  • Scopus 54
  • ???jsp.display-item.citation.isi??? 45
social impact