Modern communication terminals for wireless communications are based on an all-digital architecture wherein the incoming signal undergoes analog-to-digital conversion (ADC) at intermediate frequency (IF) followed by full-digital frequency down-conversion. Moreover, baseband digital signal processing is typically carried out at 2 samples per symbol so that the high-rate digital stream at the ADC output must be decimated down to twice the symbol rate. This paper describes the architecture of a modem for satellite communications featuring a decimating front-end. Particular emphasis is devoted to the adoption of parallel-processing solutions to overcome the inherent speed limitation of a conventional serial architecture, dictated by the technology of the digital devices. We devise herein a decimator architecture yielding a parallelization by a factor of two while bearing the same implementation complexity as the conventional schemes. Analysis and simulation of the parallelized receiver architecture with multi-level turbo-coded signal exhibit a negligible loss due to the digital front end with respect to “ideal” down-conversion and decimation.
Multi-Rate Modem Front-End for High Speed Satellite Data Transmission
GIANNETTI, FILIPPO;LUISE, MARCO
2004-01-01
Abstract
Modern communication terminals for wireless communications are based on an all-digital architecture wherein the incoming signal undergoes analog-to-digital conversion (ADC) at intermediate frequency (IF) followed by full-digital frequency down-conversion. Moreover, baseband digital signal processing is typically carried out at 2 samples per symbol so that the high-rate digital stream at the ADC output must be decimated down to twice the symbol rate. This paper describes the architecture of a modem for satellite communications featuring a decimating front-end. Particular emphasis is devoted to the adoption of parallel-processing solutions to overcome the inherent speed limitation of a conventional serial architecture, dictated by the technology of the digital devices. We devise herein a decimator architecture yielding a parallelization by a factor of two while bearing the same implementation complexity as the conventional schemes. Analysis and simulation of the parallelized receiver architecture with multi-level turbo-coded signal exhibit a negligible loss due to the digital front end with respect to “ideal” down-conversion and decimation.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
