A VLSI architecture for edge-preserving video noise reduction is proposed. It is based on a non-linear rational filter enhanced by a noise estimator for blind and dynamic adaptation to the input signal characteristics. Simulation results prove its efficiency for many noise distributions. Realized in a 0.18 um CMOS technology, the circuit allows for real-time processing of main video formats, up to 30 Hz 4CIF, with a bounded power consumption in the order of few mW.
Low-power VLSI Architecture for Adaptive Video Noise Reduction
FANUCCI, LUCA;SAPONARA, SERGIO;TERRENI, PIERANGELO
2003-01-01
Abstract
A VLSI architecture for edge-preserving video noise reduction is proposed. It is based on a non-linear rational filter enhanced by a noise estimator for blind and dynamic adaptation to the input signal characteristics. Simulation results prove its efficiency for many noise distributions. Realized in a 0.18 um CMOS technology, the circuit allows for real-time processing of main video formats, up to 30 Hz 4CIF, with a bounded power consumption in the order of few mW.File in questo prodotto:
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