To meet both flexibility and performance requirements, particularly when implementing high-end real-time image/video processing algorithms, the paper proposes to combine the application specific instruction-set processor (ASIP) paradigm with the reconfigurable hardware one. As case studies, the design of partially reconfigurable ASIP (r-ASIP) architectures is presented for two classes of algorithms with widespread diffusion in image/video processing: motion estimation and retinex filtering. Design optimizations are addressed at both algorithmic and architectural levels. Special processor concepts used to trade-off performance versus flexibility and to enable new features of post-fabrication configurability are shown. Silicon implementation results are compared to known ASIC, DSP or reconfigurable designs; the proposed r-ASIPs stand for their better performance-flexibility figures in the respective algorithmic class.
|Autori:||Saponara S; Casula M; Fanucci L|
|Titolo:||ASIP-based reconfigurable architectures for power-efficient and real-time image/video processing|
|Anno del prodotto:||2008|
|Digital Object Identifier (DOI):||10.1007/s11554-008-0084-y|
|Appare nelle tipologie:||1.1 Articolo in rivista|