Real-time and high-quality video coding is gaining a wide interest in the research and industrial community for different applications. H.264/AVC, a recent standard for high performance video coding, can be successfully exploited in several scenarios including digital video broadcasting, high-definition TV and DVD-based systems, which require to sustain up to tens of Mbits/s. To that purpose this paper proposes optimized architectures for H.264/AVC most critical tasks, Motion estimation and context adaptive binary arithmetic coding. Post synthesis results on sub-micron CMOS standard-cells technologies show that the proposed architectures can actually process in real-time 720 x 480 video sequences at 30 frames/s and grant more than 50 Mbits/s. The achieved circuit complexity and power consumption budgets are suitable for their integration in complex VLSI multimedia systems based either on AHB bus centric on-chip communication system or on novel Network-on-Chip (NoC) infrastructures for MPSoC (Multi-Processor System on Chip). (C) 2010 Elsevier B.V. All rights reserved.
|Autori:||Saponara S; Martina M; Casula M; Fanucci L; Masera G|
|Titolo:||Motion estimation and CABAC VLSI co-processors for real-time high-quality H.264/AVC video coding|
|Anno del prodotto:||2010|
|Digital Object Identifier (DOI):||10.1016/j.micpro.2010.06.003|
|Appare nelle tipologie:||1.1 Articolo in rivista|