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EnglishIP address lookup is a fundamental task for Internet routers. Because of the rapid growth of both traffic and links capacity, the time budget to process a packet continues to decrease and lookup tables unceasingly grow; therefore, new algorithms are required to improve lookup performance. However, the large density disparity on the prefix range within real lookup tables suggests a hybrid adaptive technique as effective and simple solution. Therefore, this paper presents a novel approach in which various prefix length ranges are represented with distinct data structures and stored in different memories. In this way, the different frequencies of forwarding rules can be taken in account and the memory hierarchy of real platforms can be exploited. This leads to small structures to be put in fast memory for the most dense ranges and larger structures (with a lower number of accesses) in the slower memories for the other ranges. The results remark the low number of off-chip memory accesses of our scheme and a valuable speedup.
| Titolo: | A Heuristic and Hybrid Hash-based Approach to Fast Lookup | |
| Autori interni: | ||
| Anno del prodotto: | 2009 | |
| Abstract: | IP address lookup is a fundamental task for Internet routers. Because of the rapid growth of both traffic and links capacity, the time budget to process a packet continues to decrease and lookup tables unceasingly grow; therefore, new algorithms are required to improve lookup performance. However, the large density disparity on the prefix range within real lookup tables suggests a hybrid adaptive technique as effective and simple solution. Therefore, this paper presents a novel approach in which various prefix length ranges are represented with distinct data structures and stored in different memories. In this way, the different frequencies of forwarding rules can be taken in account and the memory hierarchy of real platforms can be exploited. This leads to small structures to be put in fast memory for the most dense ranges and larger structures (with a lower number of accesses) in the slower memories for the other ranges. The results remark the low number of off-chip memory accesses of our scheme and a valuable speedup. | |
| Handle: | http://hdl.handle.net/11568/200596 | |
| ISBN: | 9781424451739 | |
| Appare nelle tipologie: | 4.1 Contributo in Atti di convegno |
File in questo prodotto:
http://hdl.handle.net/11568/200596
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