The 3D discrete cosine transform (DCT) extends the energy compaction properties of conventional 2D-DCT to integral 3D images and to the spatio-temporal coding of 2D video sequences. This paper addresses the problem of a cost-effective VLSI realization of the 3D-DCT and its inverse (IDCT). The VLSI design space is exploited at different levels of abstraction (algorithm, architecture, circuit, technology) to devise a family of 3D-DCT/IDCT macrocells that, implemented in a 0.18 μm CMOS technology, support the real-time processing of main video formats with different trade-offs between circuit complexity and power consumption. A clock-gating design strategy further reduces power consumption according to input signal statistics.

Low-Power VLSI Architectures for 3D Discrete Cosine Transform (DCT)

SAPONARA, SERGIO;FANUCCI, LUCA;TERRENI, PIERANGELO
2003

Abstract

The 3D discrete cosine transform (DCT) extends the energy compaction properties of conventional 2D-DCT to integral 3D images and to the spatio-temporal coding of 2D video sequences. This paper addresses the problem of a cost-effective VLSI realization of the 3D-DCT and its inverse (IDCT). The VLSI design space is exploited at different levels of abstraction (algorithm, architecture, circuit, technology) to devise a family of 3D-DCT/IDCT macrocells that, implemented in a 0.18 μm CMOS technology, support the real-time processing of main video formats with different trade-offs between circuit complexity and power consumption. A clock-gating design strategy further reduces power consumption according to input signal statistics.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11568/202697
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