Recent advances in high-speed acquisition of MR signals demand higher levels of performance from RF receiver chain. High-performance ADCs require a highly stable clock in terms of short-term changes defined by the jitter specification. In this note, we propose a theory for the estimation of clock jitter influence on the final image SNR. In particular, starting from a typical RF receiver chain design specification, which is required to obtain the desired SNR, we analyze the influence of clock noise on the MR signal dynamic. The entire offset frequency range (0-10 MHz OFR) is split into two intervals according to different estimation methods. The obtained results show that, in our specific application, the jitter influence does not affect the final image SNR value. The presented methodology can be easily extended to every MR application thanks to its high flexibility; in fact, the implemented concepts allow choosing, in each case, the optimal oscillator with the desired clock jitter, or quantifying the system performance degradation.

A theory for the estimation of SNR degradation caused by clock jitter in MRI systems

VANELLO, NICOLA;LANDINI, LUIGI;
2007

Abstract

Recent advances in high-speed acquisition of MR signals demand higher levels of performance from RF receiver chain. High-performance ADCs require a highly stable clock in terms of short-term changes defined by the jitter specification. In this note, we propose a theory for the estimation of clock jitter influence on the final image SNR. In particular, starting from a typical RF receiver chain design specification, which is required to obtain the desired SNR, we analyze the influence of clock noise on the MR signal dynamic. The entire offset frequency range (0-10 MHz OFR) is split into two intervals according to different estimation methods. The obtained results show that, in our specific application, the jitter influence does not affect the final image SNR value. The presented methodology can be easily extended to every MR application thanks to its high flexibility; in fact, the implemented concepts allow choosing, in each case, the optimal oscillator with the desired clock jitter, or quantifying the system performance degradation.
Hartwig, V.; Giovannetti, G.; Viti, V.; Vanello, Nicola; Landini, Luigi; Benassi, A.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11568/232743
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