The MEG experiment at PSI aims at investigating the mu(+) --> e(+) + gamma decay with improved sensitivity on the branching ratio (BR) by two orders of magnitude with respect to the previous experimental limit (BR(mu(+) --> e(+) + gamma) approximate to 10(-13)). The use of the most intense continuous muon beam world wide (approximate to 10(8) mu/s) to search for such a rare event must be accompanied by an efficient trigger system, able to suppress the huge beam-related background to sustainable rates while preserving the efficiency on signal close to unity. In order to accomplish both objectives, a digital approach was exploited by means of Field Programmable Gate Arrays (FPGA), working as a real-time processors of detector signals to perform an accurate event reconstruction within a 450 ns latency. This approach eventually turned out to be flexible enough to allow us to record calibration events in parallel with the main data acquisition and monitor the detector behavior throughout the data taking. We describe here the hardware implementation of the trigger and its main features as well: signal digitization, online waveform processing, reconstruction algorithms. A detailed description is given of the system architecture, the feature of the boards and their use. The trigger algorithms will be described in details in a dedicated article to be published afterwards.

An FPGA-based trigger system for the search of mu(+) -> e(+) + gamma decay in the MEG experiment

CEI, FABRIZIO;NICOLO', DONATO;
2013

Abstract

The MEG experiment at PSI aims at investigating the mu(+) --> e(+) + gamma decay with improved sensitivity on the branching ratio (BR) by two orders of magnitude with respect to the previous experimental limit (BR(mu(+) --> e(+) + gamma) approximate to 10(-13)). The use of the most intense continuous muon beam world wide (approximate to 10(8) mu/s) to search for such a rare event must be accompanied by an efficient trigger system, able to suppress the huge beam-related background to sustainable rates while preserving the efficiency on signal close to unity. In order to accomplish both objectives, a digital approach was exploited by means of Field Programmable Gate Arrays (FPGA), working as a real-time processors of detector signals to perform an accurate event reconstruction within a 450 ns latency. This approach eventually turned out to be flexible enough to allow us to record calibration events in parallel with the main data acquisition and monitor the detector behavior throughout the data taking. We describe here the hardware implementation of the trigger and its main features as well: signal digitization, online waveform processing, reconstruction algorithms. A detailed description is given of the system architecture, the feature of the boards and their use. The trigger algorithms will be described in details in a dedicated article to be published afterwards.
Galli, L; Cei, Fabrizio; Galeotti, S; Magazzu, C; Morsani, F; Nicolo', Donato; Signorelli, G; Grassi, M.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11568/234927
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