Prototypes of a new hybrid pixel detector and a high resistivity detector with short strips, developed by the VIPIX Collaboration and aimed at equipping the layer-0 of the SuperB vertex detector, have been tested in September 2011 with a 120 GeV pion beam at the SPS H6 beam line at CERN. They are placed at the center of a reference telescope consisting of six planes of silicon detector with a double-sided strip readout. Both the telescope and the detectors under test (DUT) are equipped with a custom-design, data-push digital readout. The main elements of the trigger and data acquisition system are two VME boards (EDRO) organized in a master-slave configuration and responsible for programming the front-end chips of both the telescope and the DUT. The master board distributes a global synchronization clock and the triggers to all devices, including two 3 x 3 analog-maps matrices placed behind the DUT and supplied with an independent readout. Both EDROs act as event-fragment builders. These are sent out to a remote PC for event building, buffering and storage. (C) 2012 Elsevier B.V. All rights reserved.

The data acquisition system of the SuperB-SVT beam test

PAOLONI, EUGENIO;
2013

Abstract

Prototypes of a new hybrid pixel detector and a high resistivity detector with short strips, developed by the VIPIX Collaboration and aimed at equipping the layer-0 of the SuperB vertex detector, have been tested in September 2011 with a 120 GeV pion beam at the SPS H6 beam line at CERN. They are placed at the center of a reference telescope consisting of six planes of silicon detector with a double-sided strip readout. Both the telescope and the detectors under test (DUT) are equipped with a custom-design, data-push digital readout. The main elements of the trigger and data acquisition system are two VME boards (EDRO) organized in a master-slave configuration and responsible for programming the front-end chips of both the telescope and the DUT. The master board distributes a global synchronization clock and the triggers to all devices, including two 3 x 3 analog-maps matrices placed behind the DUT and supplied with an independent readout. Both EDROs act as event-fragment builders. These are sent out to a remote PC for event building, buffering and storage. (C) 2012 Elsevier B.V. All rights reserved.
C., Sbarra; L., Fabbri; A., Gabrielli; F., Giorgi; A., Lusiani; Paoloni, Eugenio; G., Pellegrini; N., Semprini Cesari; S., Valentinetti; M., Villa; A., Zoccoli
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11568/293577
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